1. Field of the Invention
This invention relates generally to arrays. More specifically this invention relates to use of spare bit lines in the arrays.
2. Description of the Related Art
Electronic systems such as computer processors, personal digital assistants (PDAs), and electronic gaming systems, include large amounts of arrays to store information. Arrays dominate, in terms of area used on chip, many modern implementations of such electronic systems. A very large percentage of modern processor chip area, for example, is occupied by a first level cache, a second level, and even third level cache. Such caches are typically implemented as SRAM (Static Random Access Memory) arrays, although some processor chips are implementing one or more of the cache arrays with DRAM (Dynamic Random Access memory) arrays. In addition, electronic systems often use CAM (Content Addressable Memory) arrays, ROM (Read Only Memory) arrays, and the like. Of course, main memory used in computer systems is typically implemented a number of memory chips manufactured in DRAM technology.
During manufacture of a semiconductor chip, defects can occur that cause parts of the chip to be nonfunctional. In the case of an array, a bit line may be nonfunctional as a result of a manufacturing defect. The nonfunctional bit line may be discontinuous along a length of the bit line. The nonfunctional bit line may be shorted to a voltage supply such as VDD or ground. The nonfunctional bit line may be shorted to an adjacent bit line.
Arrays frequently have one failing bit line, and a spare bit line is used to replace the failing bit line, with data signals being routed around the failing bit line to the spare bit line during writes to the array and data being routed from the spare bit line to the proper data signals during reads.
As more bits are stored in arrays on modern semiconductor chips, resultant from an ever-increasing demand for more storage close to processing elements, the probability of multiple independent failing bit lines increases. An unrepairable array means that an expensive semiconductor chip must be discarded.
Therefore, there is a need for a method and apparatus to repair multiple independent bit line failures in an array.